In general with electronic components, and in particular when using integrated power FETs, the size of the device is directly proportional to the voltage rating of the device; The higher the breakdown and/or operating voltage of the device, the larger the silicon area that is used. As the size of devices increases, so does their cost, as well as the area and costs to implement any associated system. Traditionally, device operating voltages are selected based on the absolute maximum voltage the device can be expected to withstand, even in applications wherein it is not anticipated that the device should actually be operating at the theoretical maximum voltage level. This often results in wasted area and increased costs.
Due to these and other problems remaining in the state of the art, it would be useful and advantageous to provide circuitry designed to avoid or mitigate the occurrence of high transient voltage events, thereby facilitating the use of low voltage, smaller, circuit components.